Publications
Journal Publications
- S. Lee, T. Kang, S. Song, K. Kwon and M. P. Flynn, “An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer,” IEEE Journal of Solid-State Circuits, vol. 58, no. 4, pp. 929-938, April 2023
- S. Lee, T. Kang, J. Bell, M. Haghighat, A. Martinez and M. P. Flynn, "An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor," IEEE Journal of Solid-State Circuits, vol. 57, no. 6, pp. 1812-1823, June 2022, doi: 10.1109/JSSC.2021.3103727.
- X. Wang et al., "TAICHI: A Tiled Architecture for In-memory Computing and Heterogeneous Integration," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 559-563, Feb. 2022, doi: 10.1109/TCSII.2021.3097035.
- L. Jie, H. -W. Chen, B. Zheng and M. P. Flynn, "A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM," IEEE Journal of Solid-State Circuits, December 2021.
- L. Jie, X. Tang, J. Liu, L. Shen, S. Li, N. Sun and M. P. Flynn "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021, doi: 10.1109/OJSSCS.2021.3119910. (Invited)
- T. Kang, S. Lee, M. Haghighat, D. Abramson and M. P. Flynn, "A 650-μW 4-Channel 83-dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction," IEEE Solid-State Circuits Letters, vol. 4, pp. 158-161, 2021, doi: 10.1109/LSSC.2021.3109241.
- B. Zheng, L. Jie and M. P. Flynn, "A 6-GHz MU-MIMO Eight-Element Direct Digital Beamforming TX Utilizing FIR H-Bridge DAC," in IEEE Transactions on Microwave Theory and Techniques, June 2021.
- R. Lu, C. Weston, D. Weyer, F. Buhler, D. Lambalot and M. P. Flynn, "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver," IEEE Journal of Solid-State Circuits, May 2021.
- P. L. Brown, M. O'Shaughnessy, C. Rozell, J. Romberg, and M. P. Flynn, “A 17.8 MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network,” IEEE Journal of Solid-State Circuits, March 2021.
- L. Jie, B. Zheng, H. W. Chen and M. P. Flynn, “A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension,” IEEE Journal of Solid-State Circuits, December 2020.
- F. N. Buhler, D. K. Wehe, and M. P. Flynn, “A secure measurement unit for an inspection system used in nuclear arms-control verification,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, December 2020.
- J. M. Correll et al., "A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp. 36-44, June 2020.
- L. Jie, B. Zheng and M. P. Flynn, "A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC," in IEEE Journal of Solid-State Circuits, December 2019.
- J. Bell and M. P. Flynn, "A Simultaneous Multiband Continuous-Time Delta Sigma ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS," in IEEE Solid-State Circuits Letters, September 2019.
- F. Cai, J. M. Correll, S. H. Lee , Y. Lim, V. Bothra, Z. Zhang, M. P. Flynn and W. D. Lu, "A Fully Integrated Reprogrammable Memristor– CMOS System for Efficient Multiply–accumulate Operations," in Nature Electronics, Vol. 2, July 15, 2019, Cover Story.
- B. Zheng, L. Jie, J. Bell, Y. He, M. P. Flynn, "A Two-Beam Eight-Element Direct Digital Beamforming RF Modulator in 40-nm CMOS," in IEEE TMTT, July 2019.
- D. Weyer et al., "Design Considerations for Integrated Radar Chirp Synthesizers," in IEEE Access, January 2019.
- S. Jang, R. Lu, J. Jeong and M. P. Flynn, "A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer," in IEEE Journal of Solid-State Circuits, February 2019.
- M. B. Dayanik and M. P. Flynn, "Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System," in IEEE Journal of Solid-State Circuits, March 2018.
- S. Jang, J. Jeong, R. Lu and M. P. Flynn, "A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS," in IEEE Journal of Solid-State Circuits, January 2018.
- S. Song, K. D. Choo, T. Chen, S. Jang, M. P. Flynn and Z. Zhang, "A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link," in IEEE Transactions on Circuits and Systems I: Regular Papers, July 2018.
- N. Collins, A. Tamez, L. Jie, J. Pernillo and M. P. Flynn, "A Mismatch-Immune 12-bit SAR ADC With Completely Reconfigurable Capacitor DAC," in IEEE Transactions on Circuits and Systems II: Express Briefs, Nov. 2018.
- Y. Rajavi, M. M. Ghahramani, A. Khalili, A. Kavousian B. Kim, and M. P. Flynn, “A 48MHz Differential Crystal Oscillator with 168fs Jitter in 28nm CMOS” IEEE Journal of Solid-State Circuits, October 2017.
- J. Bell, P. Knag, S. Sun, Y Lim, T. Chen, J. Fredenburg, C. Chen, C. Zhai, A. Rocca, N. Collins, A. Tamez, J. Pernillo, J. Correll, Z. Zhang and M.P. Flynn, “A 1.5GHz 6.144Tcorrelations/s 64x64 Cross-Correlator with 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging,” IEEE Journal of Solid-State Circuits, May 2017.
- J. Jeong, N. Collins, and M. P. Flynn, "A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer with an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators," IEEE Journal of Solid-State Circuits, May 2016.
- A. E. Mendrela, J. Cho, J. A. Fredenburg, M. P. Flynn, and E. Yoon, "A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression," IEEE Journal of Solid-State Circuits, April 2016.
- H. Chae and M.P. Flynn, “A 69dB SNDR, 25MHz BW, 800MS/s Continuous-time Bandpass ΔΣ Modulator Using a Duty-cycle-controlled DAC for Low Power and Reconfigurability,” IEEE Journal of Solid-State Circuits, March 2016.
- Y. Lim and M.P. Flynn, "A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC," IEEE Journal of Solid State Circuits, December 2015.
- Y. Lim and M.P. Flynn, " A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers," IEEE Journal of Solid State Circuits, October 2015.
- H. Rhew, J. Jeong, J. Fredenburg, S. Dodani, P. Patil, and M.P. Flynn, "A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management," IEEE Journal of Solid-State Circuits, October 2014.
- H. Chae, J. Jeong, G. Manganaro, and M.P. Flynn, "A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF," IEEE Journal of Solid-State Circuits, February 2014.
- D.T. Lin, H. Chae, L. Li and M.P. Flynn, "A Low-Power Adaptive Receiver Utilizing Discrete-Time Spectrum-Sensing," IEEE Transactions on Microwave Theory and Techniques, March 2013.
- J.A. Fredenburg and M.P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE Journal of Solid-State Circuits, December 2012.
- D. Lin, L. Li, S. Farahani, and M.P. Flynn , "A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC," IEEE Transactions on Circuits and Systems I, December 2012.
- P. K. Yenduri, A.Z. Rocca, A.S. Rao, S. Naraghi, M.P. Flynn and A.C. Gilbert, "A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, September 2012.
- J. A. Fredenburg and M.P. Flynn, "Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS with Random Element Mismatch," IEEE Transactions on Circuits and Systems I, July 2012.
- J. Pernillo and M.P. Flynn, "A 1.5GS/s Flash ADC with 57.7dB SFDR & 6.4b ENOB in 90nm Digital CMOS," IEEE Transactions on Circuits and Systems II, December 2011.
- C.C. Lee and M.P. Flynn, "A 14b 23MS/s 48mW Resetting SD ADC with 87db SFDR 11.7b ENOB & 0.5mm2 Area," IEEE Transactions on Circuits and Systems I, June 2011.
- C.C. Lee and M.P. Flynn, “A SAR Assisted 2-Stage Pipeline ADC,” IEEE Journal of Solid-State Circuits, April 2011.
- J. Lee, H. Rhew, D. R. Kipke and M. P. Flynn, “A 64 Channel Programmable Closed-loop Neurostimulator with 8 Channel Neural Amplifier and Logarithmic ADC,” IEEE Journal of Solid-State Circuits, September 2010.
- S. Naraghi, M. Courcy, and M. P. Flynn, "A 9-bit, 14μW and 0.06 mm2 Pulse Position Modulation ADC in 90nm digital CMOS," IEEE Journal of Solid-State Circuits, September 2010.
- J. Lee, J. Kang, S. Park, J. Seo, J. Anders, J. Guilhereme and M. P. Flynn, "A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC," IEEE Journal of Solid State Circuits, October , 2009.
- J. Park, J. Kang, S. Park, and M. P. Flynn, "A 9Gbit/s Serial Transceiver for On-chip Global Signaling over Lossy Transmission Lines," IEEE Transactions on Circuits and Systems I, October 2009.
- M. Ferriss and M. P. Flynn, "A 14mW Fractional-N PLL modulator with a digital phase detector and frequency switching scheme," IEEE Journal of Solid-State Circuits, November 2008.
- J. Chen, M. P. Flynn, and J. Hayes, "A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13μm CMOS," IEEE Journal of Solid-State Circuits, September 2007.
- S. Park, Y. Palaskas and M. P. Flynn, "A 4 GS/s 4 bit Flash ADC in 0.18 μm CMOS," IEEE Journal of Solid-State Circuits, September 2007.
- S. Park and M. P. Flynn, "A Regenerative Comparator Structure with Integrated Inductors," IEEE Transactions on Circuits and Systems I, August 2006.
- F. Kocer and M. P. Flynn, "An RF Powered, Wireless CMOS Temperature Sensor," IEEE Sensors Journal, June 2006.
- F. Kocer and M. P. Flynn, "A New Transponder Architecture with On-Chip ADC for Long-Range Telemetry Applications," IEEE Journal of Solid-State Circuits, May 2006.
- M. P. Flynn, S. Park, and C. C. Lee, "Achieving Analog Accuracy in nanometer CMOS," International Journal of High Speed Electronics and Systems, June 2005.
- M. P. Flynn, C. Donovan, and L. Sattler, "Digital Calibration Incorporating Redundancy of Flash ADCs," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, May 2003.
- C. Donovan and M. P. Flynn, "A ‘Digital’ 6-bit ADC in 0.25μm CMOS," IEEE Journal of Solid-State Circuits, March, 2002.
- D. J. Foley and M. P. Flynn, "A Low-power 8-PAM Serial Transceiver in 0.5-/splmu/m digital CMOS," IEEE Journal of Solid-State Circuits, March 2002.
- D. J. Foley and M. P. Flynn, "CMOS DLL Based 2V, 3.2ps Jitter, 1GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE Journal of Solid-State Circuits, March 2001.
- M. P. Flynn and B. Sheahan, "A 400MSample/s 6b CMOS Folding and interpolating ADC," IEEE Journal of Solid-State Circuits, December 1998.
- M.P. Flynn and D.J. Allstot, "CMOS folding ADCs with Current-mode Interpolation," IEEE Journal of Solid-State Circuits, September 1996.
- M. P. Flynn and S. Lidholm, "A 1.2 mu m CMOS current controlled oscillator," IEEE Journal of Solid-State Circuits, July 1992.
Conference Publications
- E. Ware, J. Correll, S. Lee, and M. P. Flynn, “6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2022.
- J. Correll, L. Jie, S. Song, S. Lee, J. Zhu, W. Tang, L. Wormald, M. Chudzik, Z. Zhang, W. D. Lu, and M. P. Flynn, “An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine” IEEE Symposium on VLSI Circuits, June 2022.
- S. Lee, T. Kang, S. Song, K. Kwon, and M. P. Flynn, “An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer” IEEE Symposium on VLSI Circuits, June 2022.
- M.P. Flynn and R. Lu " Frequency Interleaved Bandpass Analog-Digital Conversion - Breaking the Bandwidth Bottleneck of Continuous-Time Delta Sigma Modulators " Government Microelectronics Conference (GOMACTech) March 2022.
- T. Kang, S. Lee, S. Song, M. R. Haghighat and M. P. Flynn, "A Multimode 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 500-502.
- M. Petryk, Z. Chen, M. P. Flynn and Z. He, “Digital signal processing application specific integrated circuit for 3D CdZnTe gamma ray detectors”, IEEE Nuclear Science Symposium and Medical Imaging Conference, October 2021.
- R. Lu and M. P. Flynn, “A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS" IEEE Symposium on VLSI Circuits, June 2021.
- T. Kang, S. Lee, M. Haghighat, D. Abramson, and M. P. Flynn, “A 650µW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction” 2020 IEEE Custom Integrated Circuits Conference (CICC), March 2021.
- M.P. Flynn, C. Weston and R. Lu "A CMOS 16-Element 28GHz Digital Beamformer with In-Package 4x4 Patch Antenna Array" Government Microelectronics Conference (GOMACTech) March 2021.
- L. Jie, H Chen, B. Zheng and M. P. Flynn, “A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer” IEEE International Solid State Circuits Conference, February 2021.
- S. Lee, T. Kang, J. Bell, M. Haghighat, A. Martinez, and M. P. Flynn, "An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy" IEEE Symposium on VLSI Circuits, June 2020.
- R. Lu, C. Weston, D. Weyer, F. Buhler, M. P. Flynn, "A 16-Element Fully Integrated 28GHz Digital Beamformer with In-Package 4×4 Patch Antenna Array and 64 Continuous-Time Band-Pass Delta-Sigma Sub-ADCs" 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2020.
- Boyi Zheng, Lu Jie, Runyu Wang, Michael P. Flynn, "A 6GHz 160MHz Bandwidth MU-MIMO Eight-Element Direct Digital Beamforming TX Utilizing FIR H-Bridge DAC" 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2020.
- M. P. Flynn, J. Jeong, S. Jang, H. Chae, D. Weyer, R. Lu and J. Bell, "Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing" 2020 IEEE Custom Integrated Circuits Conference (CICC), March 2020. (Invited)
- P. Brown, M. O' Shaugnessy, C. Rozell, J. Romberg, and M. P. Flynn, Zheng, H-W. Chen, R. Wang, M. P. Flynn, "A 17.8 MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS" 2020 IEEE Custom Integrated Circuits Conference (CICC), March 2020.
- L. Jie, B. Zheng, H-W. Chen, R. Wang, M. P. Flynn, "A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100 kHz Bandwidth ," 2020 International Solid-State Circuits Conference, (ISSCC), February 2020.
- J. Bell, M. P. Flynn, "A Simultaneous Multi-Band Continuous-Time Delta-Sigma ADC with 90MHz Aggregate Bandwidth in 40nm CMOS, " 2019 ESSCIRC, 45th European Solid-State Circuits Conference, Krakow, September 2019.
- R. Lu, S. Jang, Y. Hao, M. P. Flynn, "A 77dB-SFDR Multi-Phase-Sampling 16-Element Digital Beamformer with 64 4GS/s 100MHz-BW Continuous-Time Band-Pass ΔΣ ADCs," 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2019.
- L. Jie, B. Zheng and M. P. Flynn, "20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC," 2019 IEEE International Solid- State Circuits Conference, (ISSCC), February 2019.
- F. Buhler, D. Wehe, M. Flynn “A Side Channel Attack Immune Secure Measurement Unit for Nuclear Nonproliferation Treaty Verification with Built-in Information Barriers” IEEE Nuclear Science Symposium and Medical Imaging Conference, November, 2018.
- S. Jang, R. Lu, J. Jeong and M. P. Flynn, "A True Time Delay 16-Element 4-Beam Digital Beamformer," 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2018.
- B. Zheng, J. Bell, Y. He, L. Jie and M. P. Flynn, "A 0.19mm2128mW 0.8-1.2GHz 2-Beam 8-Element Digital Direct to RF Beamforming Transmitter in 40nm CMOS," 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2018.
- A. E. Mendrela, S.-Y. Park, M. Vöröslakos, M. P. Flynn, E. Yoon, "A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping," IEEE Symposium on VLSI Circuits, June 2018.
- D. Weyer, M. B. Dayanik, S. Jang and M. P. Flynn, "A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter," 2018 IEEE International Solid - State Circuits Conference, February 2018.
- M. P. Flynn and Y. Lim, “Pipeline and SAR ADCs for Advanced Nodes” 26th Workshop on Advances in Analog Circuit Design, March 2017.
- M. B. Dayanik, D. Weyer and M. P. Flynn “A 5GS/s 156MHz BW 70dB DR Continuous-Time Sigma-Delta Modulator with Time-Interleaved Reference Data-Weighted Averaging” 2017 IEEE Symposium on VLSI Circuits.
- Y. Lim and M.P. Flynn, “A Calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s Four-Stage Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC” 2017 IEEE Symposium on VLSI Circuits.
- F. N. Buhler, P. Brown, J. Li, T. Chen, Z. Zhang and M. P. Flynn, “A 3.43TOPS/W 48.9pJ/Pixel 50.1nJ/Classification 512 Analog Neuron Sparse Coding Neural Network with On-Chip Learning and Classification in 40nm CMOS” 2017 IEEE Symposium on VLSI Circuits.
- S. Jang, J. Jeong, R. Lu and M. P. Flynn, "A 16-element 4-beam 1GHz-IF 100MHz-bandwidth interleaved bit-stream beamformer in 40nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2017.
- D. Robertson, A. Buchwald, M.P. Flynn, H. S. Lee, U. K. Moon and B. Murmann, "Data converter reflections: 19 papers from the last ten years that deserve a second look," ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016. (Invited)
- M. P. Flynn and J. Jeong, “CMOS Bit-Stream Band-Pass Beamforming” Government Microelectronic Applications and Critial Technologies Conference, March 2016.
- F. Buhler, A. Mendrela, Y. Lim, J. Fredenburg and M. P. Flynn, "A 16-channel Noise-Shaping Machine Learning Analog-Digital Interface," 2016 IEEE Symposium on VLSI Circuits (VLSI Circuits), Honolulu, HI, 2016.
- A. Tanner, T. Gaier, B. Lambrigtsen, P. Kangaslahti, I. Ramos-Perez, M. P. Flynn, Z.Zhang, D. Austerberry, C. Ruf, D. McKague, "GeoSTAR System design and Development Update," MicroRad, April, 2016.
- K. D. Choo, J. Bell, M. P. Flynn, "Area-Efficient 1GS/s 6b SAR ADC with Charge-Injection-Cell-Based DAC," IEEE International Solid State Circuits Conf. (ISSCC), February 2016.
- M. Batuhan Dayanik, N. Collins and M. P. Flynn, "A 28.5 – 33.5GHz Fractional-N PLL Using a 3rd Order Noise Shaping Time-to-Digital Converter with 176fs Resolution," European Solid-State Circuits Conference (ESSCIRC), September 2015.
- M. M, Ghahramani, Y. Rajavi, A. Khalili, A. Kavousian,B. Kim, and M. P. Flynn, "A 192MHz Differential XO Based Frequency Quadrupler with Sub-Picosecond Jitter in 28nm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2015.
- Yong Lim, M. P. Flynn, "A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC," Solid- State Circuits Conference - (ISSCC), IEEE International, 2015.
- J. Fredenburg and M. P. Flynn, "ADC Trends and Impact on SAR ADC Architecture and Analysis," Custom Integrated Circuits Conference, September, 2015.
- Jaehun Jeong, Collins, N. , Flynn, M.P., "An IF 8-element 2-beam bit-stream band-pass beamformer," Radio Frequency Integrated Circuits Symposium (RFIC), May, 2015.
- Mendrela, A.E. ; Jihyun Cho ; Fredenburg, J.A. ; Chestek, C.A. ; M.P. Flynn; Euisik Yoon, "Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression," , Symposium on VLSI Circuits (VLSI Circuits), 2015.
- Yong Lim, Michael P. Flynn, "A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers," Solid-State Circuits Conference Digest of Technical Papers, 2014 IEEE International Solid State Circuits Conf.(ISSCC), February, 2014.
- Chunyang Zhai, Jeffrey Fredenburg, John Bell, and Michael P. Flynn, "An N-path filter enhanced low phase noise ring VCO," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HW, June, 2014.
- Hyungil Chae, Flynn, M.P., "A 69dB SNDR, 25MHz BW, 800MS/s continuous-time bandpass ΔΣ ADC using DAC duty cycle control for low power and reconfigurability," 2013 Symposium on VLSI Circuits (VLSIC), IEEE Journal of Solid-State Circuits, (Volume:49 , Issue: 2), pp. 405-415, December 11, 2013.
- Jorge Pernillo and Michael P. Flynn, "A 9b 2GS/s 45mW 2X-interleaved ADC," 2013 Proceedings of the ESSCIRC (ESSCIRC) , pp. 125-128, 16-20 Sept. , 2013.
- H. Chae, J. Jeong, G. Manganaro and M. P. Flynn, "A 12mW Low Power Continuous-time Bandpass ∑∆ Modulator with 58dB SNDR and 24MHz Bandwidth at 200MHz IF," IEEE International Solid State Circuits Conf.(ISSCC), February, 2012.
- H. Rhew, J. Park and M.P. Flynn, "A 22Gb/s, 10mm On-Chip Serial Link over Lossy Transmission Line with Resistive Termination," European Solid-State Circuits Conference (ESSCIRC), September , 2012.
- L. Li, M. A. Ferriss, and M. P. Flynn, "A 5.8GHz Digital Arbitrary Phase-Setting Type II PLL in 65nm CMOS with 2.25deg Resolution," Asia Solid-State Circuits Conference (ASSCC), November, 2012.
- J. Fredenburg, and M. P. Flynn, "A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-shaping SAR ADC," (ISSCC) IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 468-469, February, 2012.
- J. Pernillo and M. P. Flynn, "A 9b 1GS/S 27mW Two-Stage Pipeline ADC in 45nm SOI-CMOS," Asia Solid-State Circuits Conference (ASSCC), November , 2012.
- M. Ghahramani, M. Taghivand and M. P. Flynn, "A Low Voltage Sub 300uW 2.5GHz Current Reuse VCO," Asia Solid-State Circuits Conference (ASSCC), November, 2012.
- H. G. Rhew, J. Jeong, J.A. Fredenburg, S. Dodani, P. Patil, M.P. Flynn, "A Wirelessly Powered Log-based Closed-loop Deep Brain Stimulation SoC with RF telemetry for Treatment of Neurological Disorders," IEEE Symposium on VLSI Circuits,Honolulu, HI, June, 2012.
- H. G. Rhew, J. Jeong, J. A. Fredenburg, S. Dodani, P. Patil, and M. P. Flynn, "A Wirelessly Powered Log-based Closed-loop Deep Brain Stimulation SoC with Two-way Wireless Telemetry for Treatment of Neurological Disorders," VLSI Symposium on VLSI Circuits, Honolulu, HI, June, 2012.
- M. H. Ghaed, M. M. Ghahramani, G. Chen, M. Fojtik, D. Blaauw, M. P. Flynn, and D. Sylvester, "Low Power Wireless Sensor Networks for Infrastructure Monitoring," SPIE, San Diego, CA, vol. 8347, pp. 83470U, March (Invited), 2012.
- M. Ghahramani, M. Ferriss, and M. P. Flynn, "A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS," Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, June , 2011.
- D. Lin, L. Li, S. Farahani, and M.P. Flynn, "A 600MHz to 3.4GHz flexible spectrum-sensing receiver with spectrum-adaptive reconfigurable DT filtering," RFIC, June, 2011.
- 10. T. Gaier, B. Lambrigtsen, P. Kangaslahti, B. Lim, A. Tanner, D. Harding, H. Owen, M. Soria, I. O'Dwyer, C. Ruf, R. Miller, B. Block, M. Flynn, S. Whitaker , "Geostar-II: A Prototype water vapor imager/sounder for the path mission," IEEE International Geoscience and Remote Sensing Symposium, August, 2011.
- D. Lin, M. Ghahramani, and L. Li, and M. P. Flynn, "New Techniques for Efficient Flexible Wireless Transceivers in Nanometer CMOS," SPIE Annual Meeting, Orlando, FL, April , 2011.
- P. K. Yenduri, A, C. Gilbert, M. P. Flynn and S. Naraghi, "Rand PPM : A low power compressive sampling analog to digital converter," IEEE International
Conference on Acoustics, Speech, and Signal Processing, May , 2011.
- B. Rhew, J. Jeong, J. Fredenburg, and M. P. Flynn, "Ultra Low Power Microsystems Using RF Energy Scavenging," (IEDM) IEEE International Electron Devices Meeting, Washington, DC, December (Invited), 2011.
- C. Lee and M. P. Flynn, "A 12b 50MS/s 3.5mW SAR Assisted 2-Stage Pipeline ADC," IEEE Symposium on VLSI Circuits, June , 2010.
- Lin, D.T. ; Li Li ; Farahani, S. ; Flynn, M.P., "A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC," Custom Integrated Circuits Conference (CICC), September, 2010.
- M. Kurata, J. Lynch, T.,Galchev, M. P. Flynn, et al, "A two-tiered self-powered wireless monitoring system architecture for bridge health management," Proceedings of SPIE , Vol. 7649, 76490K (Invited), 2010.
- A. Tamez, J. A. Fredenburg, and Michael P. Flynn, "An Integrated 120 VAC Line Voltage Interface in Standard 0.13μm CMOS," IEEE European Solid-State Circuits Conference, September, 2010.
- D. T. Lin, L. Li, S. Farahani and M. P. Flynn, "Flexible Wireless Receiver with Software-Configurable DT FIR and IIR Filtering Embedded in a 7b 21MS/s SAR ADC," IEEE Custom Integrated Circuits Conference, September, 2010.
- J. Kang, and M. P. Flynn, "A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13µm CMOS," IEEE Symposium on VLSI Circuits, June , 2009.
- S. Naraghi, M. Courcy, and M. P. Flynn, "A 9b 14µW 0.06mm2 Pulse Position Modulation ADC in 90nm Digital CMOS," IEEE International Solid State Circuits Conf. (ISSCC), February, 2009.
- M. Ferriss, D. Lin, and M. P. Flynn, "A Fractional-N PLL modulator with flexible direct digital phase modulation," IEEE Custom Integrated Circuits Conference (CICC), September, 2009.
- J. P. Lynch, K. Kamat, V. Li, M. P. Flynn, D. Sylvester, K. Najafi, T. Gordon, M. Lepech, A. Emami-Naeini, A. Krimotat, M. Ettouney, S.Alampalli, and T. Ozdemir, "Overview of a Cyber-enabled Wireless Monitoring System for the Protection and Management of Critical Infrastructure Systems," SPIE Smart Structures and Materials, San Diego, CA, (Invited Paper), 2009.
- C. C. Lee and M. P. Flynn, "A 14b 23MS/s 48mW Resetting SD ADC with 87dB SFDR 11.7b ENOB & 0.5mm2 area," IEEE Symposium on VLSI Circuits, June , 2008.
- D. Shi, N. Behdad, J. Chen, and M. P. Flynn, "A 5GHz Fully Integrated Super-regenerative Receiver with On-chip Slot Antenna in 0.13µm CMOS," IEEE Symposium on VLSI Circuits, June, 2008.
- J. Park, J. Kang, S. Park, and M. P. Flynn, "A 9Gbit/s Serial Transceiver for On-chip Global Signaling over Lossy Transmission Lines," IEEE Custom Integrated Circuits Conference (CICC), September, 2008.
- J. Kang, D. Lin, L. Li, and M. P. Flynn, "A Reconfigurable FIR Filter Embedded in a 9b Successive Approximation ADC," IEEE Custom Integrated Circuits Conference (CICC), September, 2008.
- N. Behdad, D. Shi, W. Hong, K. Sarabandi and M. P. Flynn, "A 0.3mm2 Miniaturized X-Band On-Chip Slot Antenna in 0.13μm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June , 2007.
- M. Ferriss and M. P. Flynn, "A 14mW Fractional-N PLL modulator with a novel digital phase detector and frequency switching scheme," IEEE International Solid State Circuits Conference (ISSCC), February , 2007.
- J. Lee, S. Park, J. Kang, J. Seo, J. Anders and M. P. Flynn , "A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC," J. Lee, S. Park, J. Kang, J. Seo, J. Anders and M. P. Flynn , June , 2007.
- J. Lee, S. Park, J. Kang, J. Seo, J. Anders and M. P. Flynn , "A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC," IEEE Symposium on VLSI Circuits, June , 2007.
- I. Bogue and M. P. Flynn, "A 57dB SFDR Digitally Calibrated 500MS/s Folding ADC in 0.18µm," IEEE Custom Integrated Circuits Conference (CICC), September, 2007.
- D. Shi, and M. P. Flynn , "A Compact 5GHz Q-enhanced Standing-Wave Resonator-based Filter in 0.13μm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2007.
- D. Shi, J East and M. P. Flynn, "A Compact 5GHz Standing-Wave Resonator-based VCO in 0.13µm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2007.
- S. Park, Palaskas, A. Ravi, R. Bishop and M. Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," Custom Integrated Circuits Conference (CICC), September , 2006.
- S. Park, Y. Palaskas and M. P. Flynn, "A 4GS/s 4bit Flash ADC in 0.18m CMOS," IEEE International Solid State Circuits Conference (ISSCC), February , 2006.
- J. Chen, M. P. Flynn, and J. Hayes, "A Fully Integrated Auto-Calibrated Super-Regenerative Receiver," IEEE International Solid State Circuits Conference (ISSCC), February, 2006.
- J.Y. Park and M. P. Flynn, "A Low Jitter Multi-Phase PLL with Capacitive Coupling," Custom Integrated Circuits Conference (CICC), September, 2006.
- J. Chen, M. P. Flynn and J. Hayes, "A 3.6mW 2.4-GHz Multi-Channel Super-Regenerative Receiver in 130nm CMOS," Custom Integrated Circuits Conference (CICC), September, 2005.
- J. Chen, M. P. Flynn and J. Hayes, "A 3.6mW 2.4-GHz Multi-Channel Super-Regenerative Receiver in 130nm CMOS," Custom Integrated Circuits Conference (CICC), September, 2005.
- Kocer, F.; Flynn, M.P., "A long-range RFID IC with on-chip ADC in 0.25 μm CMOS," Radio Frequency integrated Circuits (RFIC) Symposium , Digest of Papers, IEEE, 2005.
- F. Kocer and M. P. Flynn, "A New Transponder Architecture for Long-Range Telemetry Applications," European Conference on Circuit Theory and Design, August , 2005.
- J. Park and M. P. Flynn, "Capacitively Averaged Multi-Phase LC Oscillators," International Conference on Circuits and Systems (ISCAS), , 2005.
- J. Kang, J. Park and M. P. Flynn, "Global High-Speed Signaling in Nanometer CMOS," Asia Solid State Circuits Conference (ASSCC), November, 2005.
- M. P. Flynn and J. Kang, "Global Signaling over Lossy Transmission Lines," International Conference on Computer Aided Design (ICCAD), November(Invited), 2005.
- F. Kocer and M. P. Flynn, "An Injection Locked, RF Powered, Telemetry IC in 0.25µm CMOS," IEEE Symposium on VLSI Circuits, June, 2004.
- F. Kocer and M. P. Flynn, "An RF powered, wireless temperature sensor in 0.25µm CMOS," International Symposium on Circuits and Systems, May, 2004.
- R. B. Brown, D. Sylvester, D. Blaauw, M. P. Flynn, and G. Carichner, "VLSI Design Curriculum," 2004 ASEE Annual Conference & Exposition, June, 2004.
- F. Kocer and M. P. Flynn, "Wireless, remotely powered telemetry in 0.25µm CMOS," IEEE Radio Frequency Integrated Circuits Conference (RFIC 2004), pp. 339-342, 2004.
- M. P. Flynn and I. Bogue, "Using redundancy to break the link between accuracy and speed in an ADC," Instrumentation and Measurement Technology Conference (IMTC '03), Proceedings of the 20th IEEE, Vol: 1, 2003.
- E. T. Zellers, K. D. Wise, K. Najafi, D. Aslam, R. B. Brown, Q. Y. Cai, J. Driscoll, M. P. Flynn, J. Giachino, et al., "Determinations of Complex Vapor Mixtures in Ambient Air with a Wireless Microanalytical System: Vision, Progress, and Homeland Security Applications," Technical Digest of the IEEE Conference on Technologies for Homeland Security, Waltham, MA, IEEE, Boston, pp. 92-95, November 13-14, 2002.
- C. Donovan and M. P. Flynn, "A ‘Digital’ 6-bit ADC in 0.25μm CMOS," Custom Integrated Circuits Conference, pp. 145-148, May , 2001.
- D.J. Foley and M. P. Flynn, "A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS," Custom Integrated Circuits Conference, San Diego, pp. 123-126, 2001.
- D. Foley and M. P. Flynn, "A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS," International Symposium on Circuits and Systems, Vol. 2, pp. 249-252, May, 2000.
- D. Foley and M. P. Flynn, "A 3.3V 1.6GHz Low Jitter Self Correcting DLL Based Clock Synthesizer in 0.5μm CMOS," International Symposium on Circuits and Systems, Vol. 2, pp. 249-252, May , 2000.
- D. Foley and M. P. Flynn, "CMOS DLL Based 2V, 3.2ps Jitter, 1-GHz Clock Synthesizer and Temperature Compensated Tunable Oscillator," Custom Integrated Circuits Conference, pp. 371-374, May , 2000.
- M. P. Flynn and B. Sheahan, "A 400 M Sample/s 6b CMOS Folding and interpolating ADC," International Solid-State Circuits Conference, February 1998, .
- M. P. Flynn, M. Twohig, R. Byrne, H. Reyhani and J. Ryan, "A BiCMOS Preamplifier IC for Tape Drive," Custom Integrated Circuits Conference, pp. 329-332, May 1999, .
- M. P. Flynn and S. Lidholm, "A High-Performance 1μm CMOS Current Controlled Oscillator," European Solid-State Circuits Conference, September 1991, .
- J. G. Ryan, J. Doyle, M. Buckley and M. Flynn, "A Magnetic Field Sensitive Amplifier with Temperature Compensation," International Solid-State Circuits Conference, February 1992, .
- M. Buckley, J Doyle, M. Flynn and J. Ryan, "An investigation of split-drain MAGFET and signal conditioning circuitry," Proceedings of Sensors and Their Applications V, 1991, .
- M. P. Flynn and D. J. Allstot, "CMOS folding ADCs with Current-mode Interpolation," International Solid-State Circuits Conference, February 1995, .
- P.C. Maulik, M. P. Flynn, D.J. Allstot and L.R. Carley, "Rapid Redesign of Analog Cells using Constrained Optimization Techniques," Custom Integrated Circuits Conference, May 1992, .