Deep brain stimulation (DBS) of the subthalamic nucleus is an effective therapy for numerous neurological disorders including Parkinson's disease, which affects more than 1.5m people in the US. However current treatment systems require monthly or weekly adjustment by trained clinicians.
A complete wireless receiver system combines a custom multi-band, multi-standard 65nm CMOS receiver IC with a real-time baseband demodulator on an FPGA to create a full-functioning wireless demonstration system. The demonstration showcases a system built around a highly-integrated receiver IC that captures a RF input and outputs digital baseband bitstreams.
In recent years, charge-redistribution SAR (Successive Approximation) ADCs have exhibited the highest conversion efficiencies for ADCs with moderate resolution and bandwidth. For effective resolutions beyond 10 bits or so, however, the accuracy of the SAR circuit blocks limits the overall energy efficiency of the converter.
SAR ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex.
New theory and techniques for processing information received from wireless sensor networks are being investigated for the ultimate purpose of monitoring the nation's infrastructure, including bridges, buildings and related construction.
Hybrid Sigma-Delta Pipeline ADCs offer the accuracy of noise-shaping ADCs along with the speed and Nyquist sampling of pipeline ADCs. Current state-of-the-art CMOS integrated circuit (IC) processes are ideally suited to implementing digital circuits; but they do not deliver the precision and accuracy required for high-resolution analog design.
Our goal is to investigate new approaches to analog-to-digital conversion that are suited for end-of-the-roadmap CMOS, and which also deliver orders-of-magnitude improvements in speed and energy efficiency. We break analog-to-digital conversion down to its essence and simplify the process of analog-to-digital conversion to its most basic form
The aim of this research is to develop a new architecture for a wireless transmitter with an emphasis on performing much of the analog functions in the digital domain. The proposed transmitter architecture performs direct modulation by varying a phase-locked loop (PLL) divide ratio.
A continuous-time bandpass ∑∆ modulator (CTBPSDM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC.
Reducing the power consumption and chip area of analog-to-digital converters is a big challenge in today's research since analog-to-digital converters are key building blocks in all communication, sensing, and imaging systems.
The rapidly growing wireless communication market is creating a growing demand for radio frequency (RF) transceivers. To minimize size and cost, more and more RF bands and standards have been integrated onto a single chip.
A multi-channel 2.4-GHz ISM band super-regenerative receiver implemented in 130 nm CMOS.
We present a transponder architecture for long range, remotely powered, sensor telemetry applications. Power and a reference clock are recovered from a 450 MHz incident RF signal, and data is modulated on a 900 MHz carrier.
This project proposes new scheme for long-range (~10 mm) on-chip, digital signaling in a conventional digital CMOS process. Unlike other schemes, there is no requirement for up-conversion, equalization, or special metal processing. Prototype links are faster and more energy efficient than conventional parallel busses.
This work involves developing digital calibration techniques for folding analog-to-digital converters. According to the 2001 International Technology Roadmap for Semiconductors, improved ADC technology is a key factor in developing present and future applications.