Noise Shaping SAR ADCs
In recent years, charge-redistribution SAR (Successive Approximation) ADCs have exhibited the highest conversion efficiencies for ADCs with moderate resolution and bandwidth. For effective resolutions beyond 10 bits or so, however, the accuracy of the SAR circuit blocks limits the converter's overall energy efficiency. For instance, at high resolutions, the DAC voltages become small compared to the input-referred noise of a dynamic comparator, necessitating an additional power-hungry, low-noise pre-amplifier to drive the comparator.
We introduced the noise-shaping SAR ADC architecture to decouple ADC accuracy from both the resolution of the SAR capacitor array and comparator noise. In the short time since its introduction, this pioneering technique has been very widely adopted and forms the basis of some of the world’s most efficient ADCs. In more recent work, we extend noise-shaping SAR speed by interleaving the accuracy through cascaded noise shaping.
3Z. Zhao, H.-W. Chen, S. Song, T. Kang, M. P. Flynn, “A Calibration-Free 175MHz Bandwidth 60dB SNDR 6th-order Bandpass Cascaded Time-Interleaved Noise-Shaping SAR ADC with Optimum Zero Placement” IEEE Symposium on VLSI Technology and Circuits, June 2025.
H. -W. Chen, S. Lee and M. P. Flynn, "An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer," in IEEE Journal of Solid-State Circuits, vol. 59, no. 4, pp. 1171-1183, April 2024.
S. Lee, T. Kang, S. Song, K. Kwon and M. P. Flynn, "An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer," in IEEE Journal of Solid-State Circuits, vol. 58, no. 4, pp. 929-938, April 2023.
H.W. Chen, S. Lee, and M. P. Flynn, "A 0.024mm2 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM)" IEEE Symposium on VLSI Circuits, June 2023.
S. Lee, T. Kang, S. Song, K. Kwon, and M. P. Flynn, “An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer” IEEE Symposium on VLSI Circuits, June 2022. (Best student paper)
L. Jie, B. Zheng, H. W. Chen and M. P. Flynn, “A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension,” IEEE Journal of Solid-State Circuits, December 2020.
L. Jie, H. -W. Chen, B. Zheng and M. P. Flynn, "A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM," IEEE Journal of Solid-State Circuits, December 2021.
L. Jie, X. Tang, J. Liu, L. Shen, S. Li, N. Sun and M. P. Flynn "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021, doi: 10.1109/OJSSCS.2021.3119910. (Invited)
L. Jie, B. Zheng and M. P. Flynn, "A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC," in IEEE Journal of Solid-State Circuits, December 2019.
L. Jie, B. Zheng, H-W. Chen, R. Wang, M. P. Flynn, "A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100 kHz Bandwidth ," 2020 International Solid-State Circuits Conference, (ISSCC), February 2020.
L. Jie, B. Zheng and M. P. Flynn, "20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC," 2019 IEEE International Solid- State Circuits Conference, (ISSCC), February 2019.
J.A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE Journal of Solid-State Circuits, December 2012.
J. Fredenburg, and M. P. Flynn, "A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-shaping SAR ADC," (ISSCC) IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 468-469, February, 2012.
H. -W. Chen, S. Lee and M. P. Flynn, "An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer," in IEEE Journal of Solid-State Circuits, vol. 59, no. 4, pp. 1171-1183, April 2024.
S. Lee, T. Kang, S. Song, K. Kwon and M. P. Flynn, "An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer," in IEEE Journal of Solid-State Circuits, vol. 58, no. 4, pp. 929-938, April 2023.
H.W. Chen, S. Lee, and M. P. Flynn, "A 0.024mm2 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM)" IEEE Symposium on VLSI Circuits, June 2023.
S. Lee, T. Kang, S. Song, K. Kwon, and M. P. Flynn, “An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer” IEEE Symposium on VLSI Circuits, June 2022. (Best student paper)
L. Jie, B. Zheng, H. W. Chen and M. P. Flynn, “A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension,” IEEE Journal of Solid-State Circuits, December 2020.
L. Jie, H. -W. Chen, B. Zheng and M. P. Flynn, "A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM," IEEE Journal of Solid-State Circuits, December 2021.
L. Jie, X. Tang, J. Liu, L. Shen, S. Li, N. Sun and M. P. Flynn "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021, doi: 10.1109/OJSSCS.2021.3119910. (Invited)
L. Jie, B. Zheng and M. P. Flynn, "A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC," in IEEE Journal of Solid-State Circuits, December 2019.
L. Jie, B. Zheng, H-W. Chen, R. Wang, M. P. Flynn, "A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100 kHz Bandwidth ," 2020 International Solid-State Circuits Conference, (ISSCC), February 2020.
L. Jie, B. Zheng and M. P. Flynn, "20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC," 2019 IEEE International Solid- State Circuits Conference, (ISSCC), February 2019.
J.A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE Journal of Solid-State Circuits, December 2012.
J. Fredenburg, and M. P. Flynn, "A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-shaping SAR ADC," (ISSCC) IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 468-469, February, 2012.