Flynn Group at VLSI 2017

The Flynn Group presented three papers at the VLSI Symposium in Kyoto in June.

1. M. B. Dayanik, D. Weyer and M. P. Flynn “A 5GS/s 156MHz BW 70dB DR Continuous-Time Sigma-Delta Modulator with Time-Interleaved Reference Data-Weighted Averaging” 2017 IEEE Symposium on VLSI Circuits
   
   
2. Y. Lim and M.P. Flynn, “A Calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s Four-Stage Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC” 2017 IEEE Symposium on VLSI Circuits
   
   
3. F. N. Buhler, P. Brown, J. Li, T. Chen, Z. Zhang and M. P. Flynn, “A 3.43TOPS/W 48.9pJ/Pixel 50.1nJ/Classification 512 Analog Neuron Sparse Coding Neural Network with On-Chip Learning and Classification in 40nm CMOS” 2017 IEEE Symposium on VLSI Circuits