Congratulations to 2018 Graduates from the Flynn Group!!
Sunmin Jang, Ph.D.
A CMOS Digital Beamforming Receiver
Abstract: As the demand for high speed communication is increasing, 5G wireless is aiming to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming is more accurate, provides multiple simultaneous beams without an SNR penalty, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, beam squinting errors, and ADC non-linearity. First, we address the power and area challenge by combining Interleaved Bit-Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting issue. Third, we present a new current-steering DAC architecture that improves ADC linearity. To summarize, a prototype 16-element, 4-independent beam, 1 GHz center frequency, 100 MHz bandwidth prototype true time delay digital beamformer achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512. The measured beam patterns are near-ideal for both conventional and adaptive beamforming. Despite the high performance, the prototype occupies only 0.29 mm2 and consumes 453 mW.
Daniel Weyer, Ph.D.
Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters
Abstract: Automotive radar applications have spurred the development of frequency-modulated continuous-wave (FMCW) radar. The radar performance depends on high-quality signal sources for chirp generation, requiring fast-settling and low-phase-noise chirp synthesizers. Fractional-N phase locked loops (PLLs) are an effective tool to generate FMCW waveforms, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Digital synthesizer PLLs offer greater flexibility and area efficiency than their analog counterparts, but their close-in phase noise suffers from the limited resolution of conventional time-to-digital converters (TDCs). This work presents digital FMCW chirp synthesizer PLLs based on noise-shaping TDCs that leverage state-of-the-art modulator techniques. First, we describe an 18-to-22GHz chirp synthesizer with a noise-shaping TDC that combines a conventional phase detector with a third-order modulator. Second, we introduce a noise-shaping TDC based on a continuous-time bandpass modulator. The bandpass TDC samples a sinusoidal PLL reference and relies on digital down-conversion. Using this TDC, we design a 36-to-38GHz digital chirp synthesizer PLL. A 40nm CMOS prototype achieves a measured close-in phase noise of -85dBc/Hz at a 100kHz offset for wide loop bandwidths >1MHz. It effectively generates fast (500MHz/55s) and precise (824kHzrms frequency error) triangular chirps for FMCW radar applications.
Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters
Abstract: Automotive radar applications have spurred the development of frequency-modulated continuous-wave (FMCW) radar. The radar performance depends on high-quality signal sources for chirp generation, requiring fast-settling and low-phase-noise chirp synthesizers. Fractional-N phase locked loops (PLLs) are an effective tool to generate FMCW waveforms, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Digital synthesizer PLLs offer greater flexibility and area efficiency than their analog counterparts, but their close-in phase noise suffers from the limited resolution of conventional time-to-digital converters (TDCs). This work presents digital FMCW chirp synthesizer PLLs based on noise-shaping TDCs that leverage state-of-the-art modulator techniques. First, we describe an 18-to-22GHz chirp synthesizer with a noise-shaping TDC that combines a conventional phase detector with a third-order modulator. Second, we introduce a noise-shaping TDC based on a continuous-time bandpass modulator. The bandpass TDC samples a sinusoidal PLL reference and relies on digital down-conversion. Using this TDC, we design a 36-to-38GHz digital chirp synthesizer PLL. A 40nm CMOS prototype achieves a measured close-in phase noise of -85dBc/Hz at a 100kHz offset for wide loop bandwidths >1MHz. It effectively generates fast (500MHz/55s) and precise (824kHzrms frequency error) triangular chirps for FMCW radar applications.
Adam Mendrela, Ph.D.
Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes
Abstract: Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. Such systems have been employed for basic neuroscience research, therapeutic medical devices, and other brain-machine interface applications. Further development and dissemination are hindered by several system-level challenges. First, compact, power efficient, and high-channel-count solutions are needed to provide high performance functionality in wireless and chronic deployment. Second, bidirectional interfaces inherently suffer from large unwanted artifact noise during simultaneous recording and stimulation. This dissertation attempts to solve the problem of how to reduce noise and artifacts in bidirectional interfaces without greatly sacrificing efficiency and small form factor. Three ASIC-based prototypes are developed to address the different facets of this challenge. First, a front-end stimulation artifact cancellation scheme is introduced to efficiently remove artifacts in electrical stimulation and recording systems. The second prototype focuses on the miniaturization of a headstage system for high-precision optogenetic stimulation and electrophysiological recording. Finally, an optical pulse shaping scheme is developed for an opto-electrophysiology interface IC to reduce stimulation artifacts in integrated µLED optoelectrodes.
Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes
Abstract: Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. Such systems have been employed for basic neuroscience research, therapeutic medical devices, and other brain-machine interface applications. Further development and dissemination are hindered by several system-level challenges. First, compact, power efficient, and high-channel-count solutions are needed to provide high performance functionality in wireless and chronic deployment. Second, bidirectional interfaces inherently suffer from large unwanted artifact noise during simultaneous recording and stimulation. This dissertation attempts to solve the problem of how to reduce noise and artifacts in bidirectional interfaces without greatly sacrificing efficiency and small form factor. Three ASIC-based prototypes are developed to address the different facets of this challenge. First, a front-end stimulation artifact cancellation scheme is introduced to efficiently remove artifacts in electrical stimulation and recording systems. The second prototype focuses on the miniaturization of a headstage system for high-precision optogenetic stimulation and electrophysiological recording. Finally, an optical pulse shaping scheme is developed for an opto-electrophysiology interface IC to reduce stimulation artifacts in integrated µLED optoelectrodes.