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Research

Bandpass Sigma-Delta ADCs

Hyungil Chae
Picture
A continuous-time bandpass ∑∆ modulator (CTBPSDM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC]. However, conventional CTBPSDMs suffer from large power consumption and occupy large area. CTBPSDMs based on LC are large, while biquad-based resonators are also large and suffer from high power consumption because two amplifiers are usually required in each resonator. The fact that there are typically twice as many feedback paths compared to a lowpass ∑∆ modulator with the same bandwidth and performance also increases power consumption, area and complexity. This paper presents a novel power-efficient resonator with a single amplifier and also introduces a simplified architecture utilizing return-to-zero (RZ) and half-clock-delayed return-to-zero (HZ) pulses to solve the power and complexity problems. 

A 800MS/s low power 4th-order continuous-time bandpass ∑∆ modulator prototype has a 24MHz bandwidth at 200MHz IF. A novel power-efficient resonator with a single amplifier is used as a loopfilter, and a new 4th-order architecture is introduced for system simplicity and low power. This modulator shows 58dB SNDR, 60dB DR and 65dB IMD, and a total power consumption of 12mW. The total die area in 65nm CMOS is 0.2mm2.


J. Fredenburg and M. P. Flynn, “A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC” IEEE International Solid State Circuits Conf. (ISSCC), February 2012.

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