Digitally Calibrated Moderate Resolution ADCs
This work involves developing digital calibration techniques for folding analog-to-digital converters. According to the 2001 International Technology Roadmap for Semiconductors, improved ADC technology is a key factor in developing present and future applications. The switched-capacitor (SC) pipeline technique is the most popular method of implementing moderate resolution ADCs. However, the advantages of CMOS, which originally made SC circuits feasible, are being eroded by process scaling. Good switches and opamps are becoming increasingly difficult to design, and the growing gate leaking of deep submicron MOSFETs is causing difficulty. Traditional ADC schemes do not work well with supply voltages of 1.8V and below. Furthermore, the performance required by present and future wireless and IT applications will not be met by the present-day ADC circuits techniques. Traditional ADC schemes are highly dependent on analog circuit performance, in particular on device matching. Because of the high analog content of these designs, these circuits are very difficult to modify or port to other processes. Because digital circuits scale well, a digital offset technique was developed. It reduces the amount of analog design involved, since this folding ADC is dominated by digital circuitry.